This invention relates to processes for electrically isolating semiconductor devices and components in monolithic integrated circuits. In particular, the invention is a process for forming fully recessed, planarized dielectric isolation structures such as field oxides. The process involves the selective deposition of organosilicon material into trenches or depressions, followed by conversion of the organosilicon to oxide.
For some time, dielectric isolation has been a preferred technology for isolating integrated circuits and their constituent devices and elements. Integrated circuit isolation by the so-called local oxidation of silicon (LOCOS) has been known for a number of years, as have its problems. The well-known limitations of the LOCOS process include several factors which may limit its applicability to small geometry, highly dense VLSI structures. These limitations include the lateral oxide diffusion and oxidation formation (the so-called "bird's beak" configuration) beneath the nitride oxidation mask. This enlargement of the isolation field oxide and the associated encroachment into the active regions limits the percentage of chip surface area which is available for device formation. Also, the characteristic non-planar semi-recessed surface topography and the rough surface topography of the bird's head regions hinder metallization coverage as well as the high resolution photolithographic operations which are required to fabricate VLSI circuits.
In contrast to LOCOS isolation, trench isolation technology has the potential advantages of small width-to-depth ratios, relative process simplicity, well-defined vertical wall isolation regions and surface planarity. Typical trench isolation processes involve etching grooves about 0.6 to 6 micrometers deep into the semiconductor substrate, filling the grooves with a suitable dielectric material and performing a planarization operation. The deposited dielectric material typically is undoped silicon dioxide or polysilicon. However, like other VLSI features, the width of isolation trenches must be scaled downward to near micrometer and even submicrometer size to achieve the densities required in VLSI and future monolithic integrated circuit technologies.
Several approaches have been proposed which have as their purpose the control or elimination of the problems associated with the LOCOS and trench technologies. These approaches are summarized below.